Exploit Methods/Userspace data usage

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(Mitigations)
(Mitigations)
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|-
 
| v7 32-bit LPAE
 
| v7 32-bit LPAE
| future: CONFIG_CPU_TTBR0_PAN ([http://marc.info/?l=linux-arm-kernel&m=144308911409429&w=2 Catalin's series])
+
| future: CONFIG_ARM64_SW_TTBR0_PAN ([http://www.openwall.com/lists/kernel-hardening/2016/09/13/3 Catalin's series])
 
|-
 
|-
 
| v8.0 32-bit
 
| v8.0 32-bit
| future: CONFIG_CPU_TTBR0_PAN
+
| future: CONFIG_ARM64_SW_TTBR0_PAN
 
|-
 
|-
 
| v8.0 64-bit
 
| v8.0 64-bit
| future: CONFIG_CPU_TTBR0_PAN
+
| future: CONFIG_ARM64_SW_TTBR0_PAN
 
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| v8.1 (since December 2014)
 
| v8.1 (since December 2014)

Revision as of 03:46, 15 September 2016

Details

Sometimes an attacker won't be able to control the instruction pointer directly, but they will be able to redirect the dereference a structure or other pointer. In these cases, it is easiest to aim at malicious structures that have been built in userspace to perform the exploitation.

Note that this is a superset that includes Userspace execution. If we can protect against userspace access, we'll also be protecting against userspace execution.

Examples

Mitigations

  • hardware segmentation: SMAP (x86), PAN (arm, arm64), Domains (arm)
  • emulated PAN (memory segmentation via segments, Domains, page table swapping, PCID, etc. e.g. PAX_MEMORY_UDEREF)

Right now, the upstream options available for Privileged Access Never (PAN) are:

CPU Feature Name
ARM v7 32-bit non-LPAE CONFIG_CPU_SW_DOMAIN_PAN
v7 32-bit LPAE future: CONFIG_ARM64_SW_TTBR0_PAN (Catalin's series)
v8.0 32-bit future: CONFIG_ARM64_SW_TTBR0_PAN
v8.0 64-bit future: CONFIG_ARM64_SW_TTBR0_PAN
v8.1 (since December 2014) hardware PAN
x86 pre-late-Broadwell nothing
Broadwell+ (since October 2014) hardware PAN (SMAP)
s/390 hardware PAN (Address Spaces)
powerpc nothing?
MIPS nothing (could use ASID switching?)
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