[PATCH 01/17] Fix "x86/alternatives: Lockdep-enforce text_mutex in text_poke*()"

[Nadav Amit]

> On Jan 17, 2019, at 3:19 PM, H. Peter Anvin <hpa at zytor.com> wrote:
> 
>> I think we have three subcases:
>> 
>> 1. Early, UP, or under stop_machine();
>> 2. Atomic and aligned;
>> 3. Breakpoint.
>> 
>> My proposed algorithm should remove the need for a fixup which should help this interface, too.
>> 
>> The specific alignment needed for #2 is started by the hardware people to be not crossing 16 bytes (NOT a cache line) on any CPU we support SMP on and, of course, being possible to do atomically do on the specific CPU (note that we *can* do a redundantly large store of existing bytes, which adds flexibility.)
>> 
>> To the best of my knowledge any CPU supporting SSE can do an atomic (for our purposes) aligned 16-byte store via MOVAPS; of course any CPU with cx16 can do it without SSE registers. For older CPUs we may be limited to 8-byte stores (cx8) or even 4-byte stores before we need to use the breakpoint algorithm.
> 
> Sending to a restricted list, because I don't actually know how publicly
> known this is, but it is known there are operating systems in the field
> already which rely on the 16-byte atomicity guarantee.

Hmm. I don’t know how restricted the list is, considering you left "LSM list”.
;-)

Anyhow, I don’t know whether it changes things much. If you patch an MMIO
accessing instruction, which is executed on top of KVM - things might break.
IMHO, the very least hypervisors vendors should be informed before
implementing such change.